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INTEGRATED CIRCUITS
DATA SHEET
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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4737B HEF4737V LSI Quadruple static decade counters
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Quadruple static decade counters
DESCRIPTION The HEF4737B and HEF4737V are static quadruple decade counters for frequencies from 0 to 10 MHz. The counters are supplied with an extra overload flip-flop giving a total count capability of 19 999. The counter has the following inputs and outputs: a count input (CP), an asynchronous reset input (MR), an asynchronous preset input (PL), a transfer input (T), an output enable input (EO) (which controls the BCD outputs), the digit select inputs (SA, SB, SC) (which perform selection of the contents of the latches to the 3-state BCD outputs (O0 to O3)), and the carry outputs (CO2 to CO5) (which give the carry signals of the decades except from the first decade).
HEF4737B HEF4737V
The complementary MOS structure gives the devices very low stand-by and operating dissipation. Operating from a single supply voltage all outputs can drive one standard TTL input without interface circuitry under all specified operating conditions. The BCD digit outputs are LOCMOS 3-state outputs. The high impedance off-state feature allows common busing of the outputs. The counters are supplied with asynchronous reset and preset to 19 999 facilities making them suitable for counter and time base applications. All carry signals are available except from the first decade. Schmitt-trigger action in the inputs makes the circuit highly tolerant to slower input rise and fall times. Recommended supply voltage range for HEF4737B is 3 to 15 V and for HEF4737V is 4,5 to 12,5 V.
HEF4737BP; HEF4737BD;
HEF4737VP(N); 18-lead DIL plastic (SOT102-1) HEF4737VD(F); 18-lead DIL ceramic (SOT133B)
( ): Package Designator North America SUPPLY VOLTAGE RATING HEF4737B Fig.1 Pinning diagram. HEF4737V -0,5 to 18 -0,5 to 18 RECOMMENDED OPERATING 3,0 to 15,0 4,5 to 12,5 V V
PINNING CP MR PL T SA, SB, SC EO O0 to O3 CO2 to CO5 count input asynchronous reset input asynchronous preset input transfer input digit select inputs output enable input BCD outputs carry outputs
FAMILY DATA, IDD LIMITS category LSI See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Quadruple static decade counters
HEF4737B HEF4737V
Fig.2 Block diagram.
FUNCTIONAL DESCRIPTION Input signals
Preset input (PL)
This is an asynchronous preset. When MR is LOW a HIGH at the PL input will preset the counter to 19 999 independent of the level at the count input.
Count input (CP)
The signal to be counted is applied to this input. When PL and MR are LOW the contents of the counter increments by one at a LOW to HIGH transition of CP.
Transfer input (T)
A HIGH level applied to this input allows the information held by the counter to pass to the latches.
Reset input (MR)
This is an asynchronous reset. A HIGH level applied to this input will reset the counter to zero independent of the level at the count input and preset input. January 1995 3
Output enable input (EO)
A HIGH level at this input enables the BCD outputs and information can be read out of the latches using the
Philips Semiconductors
Product specification
Quadruple static decade counters
multiplexer. A LOW level at this input disables the BCD outputs making them floating (high impedance off-state). Output signals
HEF4737B HEF4737V
The carry outputs are active LOW outputs.
Digit select inputs (SA, SB, SC)
SA L H L H X Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. When D5 is selected, the contents of D5 is available at O0 and O1, O2 and O3 are LOW. 5. LSD = least significant divider 6. MSD = most significant divider SB L L H H X SC L L L L H selects D1 (LSD) selects D2 selects D3 selects D4 selects D5 (MSD)
Carry output CO2
When the contents of the first two decades of the counter are both 9 then the CO2 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first two decades are zero. CO2 is LOW when the contents of the counter are: 00 099, 00 199, 00 299 etc.
Carry output CO3
When the contents of the first three decades of the counter are all 9 then the CO3 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first three decades are zero. CO3 is LOW when the contents of the counter are 00 999, 01 999, 02 999 etc.
Carry output CO4
When the contents of the first four decades of the counter are all 9 then the CO4 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first four decades are zero. CO4 is LOW when the contents of the counter are 09 999 and 19 999. The carry signals CO2 , CO3 and CO4 are suppressed while the preset is active. A HIGH to the preset input sets the counter to 19 999 but the carry signals remain HIGH until preset input returns to LOW, then the carry outputs will also become LOW.
Carry output CO5
When the content of the counter is 10 000 the CO5 output becomes LOW. It returns to HIGH when the content of the counter is zero.
Digit outputs (O0 to O3)
The digit outputs give the contents of the selected latch. The output is in the form of BCD, positive logic.
January 1995
4
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Quadruple static decade counters HEF4737B HEF4737V
Philips Semiconductors
Product specification
Quadruple static decade counters
HEF4737B HEF4737V
The values given at VDD = 15 V in the following d.c. and a.c. characteristics, are not applicable to the HEF4737V, because of its reduced supply voltage range. DC CHARACTERISTICS VSS = 0 V Tamb (C) VDD V Input leakage current at VI = 0 or VDD Output (sink) current LOW Output (source) current HIGH Output (source) current HIGH 3-state output leakage current VO = 0 or VDD 10 15 IOZ - - 1,6 1,6 - - 1,6 1,6 - - 12 12 A A 5 2,5 -IOH 3,0 - 2,5 - 2,0 - mA 10 15 4,75 10 15 5 10 15 4,6 9,5 13,5 -IOH 0,4 0,5 1,5 IOL IIN - - 1,6 2,5 7,0 0,96 2,4 7,0 - - - - - - - - - - 1,6 2,3 6,0 0,80 2,0 6,0 0,3 0,3 - - - - - - - - 1,4 1,7 4,0 0,65 1,6 4,5 1 1 - - - - - - A A mA mA mA mA mA mA VOH V VOL V SYMBOL -40 MIN. MAX. + 25 MIN. MAX. + 85 MIN. MAX.
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 15 pF; input transition times 20 ns VDD V Propagation delays CP On (D1 selected) HIGH to LOW LOW to HIGH CP On (D5 selected) HIGH to LOW LOW to HIGH 5 10 15 5 10 15 5 10 15 5 10 15 tPLH tPHL tPLH tPHL 320 120 90 320 120 90 620 330 250 620 330 250 640 240 180 640 240 180 1240 660 500 1240 660 500 ns ns ns ns ns ns ns ns ns ns ns ns 308 ns + (0,24 ns/pF) CL 125 ns + (0,10 ns/pF) CL 86 ns + (0,07 ns/pF) CL 296 ns + (0,48 ns/pF) CL 110 ns + (0,20 ns/pF) CL 82 ns + (0,15 ns/pF) CL 608 ns + (0,24 ns/pF) CL 325 ns + (0,10 ns/pF) CL 246 ns + (0,07 ns/pF) CL 596 ns + (0,48 ns/pF) CL 320 ns + (0,20 ns/pF) CL 242 ns + (0,15 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
Quadruple static decade counters
HEF4737B HEF4737V
MIN. TYP. MAX. 220 440 220 170 400 220 170 700 320 240 700 320 240 400 160 110 400 160 110 440 180 120 440 180 120 980 400 120 520 220 170 700 320 240 700 320 240 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TYPICAL EXTRAPOLATION FORMULA 208 ns + (0,24 ns/pF) CL 105 ns + (0,10 ns/pF) CL 81 ns + (0,07 ns/pF) CL 196 ns + (0,48 ns/pF) CL 100 ns + (0,20 ns/pF) CL 77 ns + (0,15 ns/pF) CL 338 ns + (0,24 ns/pF) CL 155 ns + (0,10 ns/pF) CL 116 ns + (0,07 ns/pF) CL 326 ns + (0,48 ns/pF) CL 150 ns + (0,20 ns/pF) CL 112 ns + (0,15 ns/pF) CL 188 ns + (0,24 ns/pF) CL 75 ns + (0,10 ns/pF) CL 51 ns + (0,07 ns/pF) CL 176 ns + (0,48 ns/pF) CL 70 ns + (0,20 ns/pF) CL 47 ns + (0,15 ns/pF) CL 208 ns + (0,24 ns/pF) CL 85 ns + (0,10 ns/pF) CL 56 ns + (0,07 ns/pF) CL 196 ns + (0,48 ns/pF) CL 80 ns + (0,20 ns/pF) CL 52 ns + (0,15 ns/pF) CL 478 ns + (0,24 ns/pF) CL 195 ns + (0,10 ns/pF) CL 56 ns + (0,07 ns/pF) CL 236 ns + (0,48 ns/pF) CL 100 ns + (0,20 ns/pF) CL 77 ns + (0,15 ns/pF) CL 326 ns + (0,48 ns/pF) CL 150 ns + (0,20 ns/pF) CL 112 ns + (0,15 ns/pF) CL 338 ns + (0,24 ns/pF) CL 155 ns + (0,10 ns/pF) CL 116 ns + (0,07 ns/pF) CL
VDD V CP CO2 HIGH to LOW 5 10 15 5 LOW to HIGH Propagation delays CP CO5 HIGH to LOW 5 10 15 5 LOW to HIGH Sn On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH T On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW PL On LOW to HIGH MR COn LOW to HIGH PL COn HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 10 15 10 15
SYMBOL
tPHL
110 85 220
tPLH
110 85 350
tPHL
160 120 350
tPLH
160 120 200
tPHL
80 55 200
tPLH
80 55 220
tPHL
90 60 220
tPLH
90 60 490
tPHL
200 60 260
tPLH
110 85 350
tPLH
160 120 350
tPHL
160 120
January 1995
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Philips Semiconductors
Product specification
Quadruple static decade counters
HEF4737B HEF4737V
MIN. TYP. MAX. 35 70 36 30 100 60 50 ns ns ns ns ns ns TYPICAL EXTRAPOLATION FORMULA 15 ns + 9 ns + 8 ns + 15 ns + 13 ns + 13 ns + (0,40 ns/pF) CL (0,18 ns/pF) CL (0,13 ns/pF) CL (0,70 ns/pF) CL (0,33 ns/pF) CL (0,23 ns/pF) CL
VDD V Output transition times; any output HIGH to LOW LOW to HIGH 3-state propagation delays Output disable times EO On HIGH 5 10 15 5 LOW Output enable times EO On HIGH 5 10 15 5 LOW Maximum CP pulse width; LOW Minimum MR pulse width; HIGH Minimum PL pulse width; HIGH Minimum T pulse width; HIGH Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 10 15 5 10 15 5 10 15
SYMBOL
tTHL
18 15 50
tTLH
30 25
60 tPHZ 35 25 60 tPLZ 35 25 90 tPZH 40 30 90 tPZL 160 tWCPL 60 50 100 tWMRH 50 40 120 tWPLH 60 50 100 tWTH 40 36 3 fmax 8 10 40 30 80 30 25 50 25 20 60 30 25 50 20 18 6 16 20
120 70 50 120 70 50 180 80 60 180 80 60
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
January 1995
8
Philips Semiconductors
Product specification
Quadruple static decade counters
HEF4737B HEF4737V
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (W) 950 fi + (foCL) x VDD2 4 200 fi + (foCL) x VDD 11 200 fi + (foCL) x VDD
2 2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
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